基本信息

書名：現代應用集成電路設計(Modern ASIC Design)(英文版)

定價：120.00元

作者：周電

齣版社：科學齣版社

齣版日期：2011-07-01

ISBN：9787030317667

字數：

頁碼：

版次：1

裝幀：平裝

開本：16開

商品重量：0.640kg

編輯推薦

本書介紹應用集成電路設計的整體流程以及流程涉及的每個步驟，這些步驟之間的內在關係，以及如何使用工業化的實際的集成電路計算機輔助設計軟件完成設計任務。本書的一個突齣特點是使用一個實際的應用設計例子，有限響應濾波器的設計，引導讀者走通設計的細節。這樣一個設計實例使得讀者獲得**手的設計經驗和使用工業化計算機輔助設計軟件的知識。書中附帶瞭這個設計案例的硬件描述語言代碼以供參考。

內容提要

本書基於作者周電在美國大學十幾年教授“現代應用集成電路設計”課程的手稿整理而成，主要內容包括應用集成電路設計流程、設計指標定義和規範、邏輯電路設計、物理設計、時間功耗性能分析及驗證測試。讀者需要有數字集成電路和硬件描述語言（VHDL）的基礎知識。按照具體課程設置的要求，本書可用於一個學期的教學內容，包括應用集成電路設計流程、設計指標定義和規範、邏輯電路設計及物理設計。關於集成電路發展的前沿問題，本書在第7章和第8章中以研究課題為背影介紹瞭基礎知識。
本書可作為電子和計算機工作專業的大學四年級或碩士研究生教材，也適於集成電路設計的專業人員參考閱讀。

目錄

PrefaceChapter 1 Introduction 1.1 History of Integrated Circuits 1.2 Roadmap of IC Technology 1.3 ASIC 1.4 Design Flow 1.5 CAD Tools 1.6 AnASIC Design Project MSDAP 1.7 How to Use This Book 1.8 Summery 1.9 Problems ReferencesChapter 2 VLSI Design Perspective and Flow 2.1 Introduction 2.2 VLSI Technology Trend 2.3 SoC 2.4 Methodology for Custom and Semi-custom IC Design 2.4.1 Gate array 2.4.2 Standard cell 2.4.3 FPGA 2.5 Design Domain and Perspective 2.6 Design Flow 2.7 Design Task 2.8 Summary 2.9 Problems ReferencesChapter 3 Specification Development 3.1 Introduction 3.2 AnASIC Project MSDAP 3.3 An Overall View of the Specific Requirement 3.3.1 The required putation method by the MSDAP 3.3.2 Additional information for the specification 3.4 The System Setting 3.5 I/O Interface and Pins 3.5.1 Pins and their assignments 3.5.2 Signal format and waveform 3.6 Other Issues of the Specification 3.7 Summary 3.8 Problems ReferencesChapter 4 Architecture Design 4.1 Introduction 4.2 Datapath Structure 4.2.1 Single processor sequential structure 4.2.2 Multi-processor parallel structure 4.3 Functional Blocks and IPs 4.3.1 IP core 4.3.2 Functional blocks in the MSDAP architecture 4.4 Time Budget and Scheduling 4.5 A Sample Architecture of the MSDAP Project 4.5.1 An architecture sample 4.5.2 Time budget justification of the proposed architecture 4.6 Summary 4.7 Problems ReferencesChapter 5 Logic and Circuit Design 5.1 Introduction 5.2 Combinational Logics 5.2.1 Decoder 5.2.2 Encoder 5.2.3 Multiplexer 5.2.4 Arithmetic logic blocks 5.3 Sequential Logics 5.3.1 Latch and flip-flop 5.3.2 Shift register 5.3.3 Counter 5.3.4 FSM 5.4 Datapath 5.5 Asynchronous Circuit 5.6 Summery 5.7 Problems ReferencesChapter 6 Physical Design 6.1 Introduction 6.2 Design Rules 6.3 Floorplan 6.4 Routing 6.4.1 Global routing 6.4.2 Local routing 6.5 Physical Layout Verification 6.5.1 DRC 6.5.2 XOR check 6.5.3 Antenna check 6.5.4 ERC 6.5.5 LVS check 6.6 Clock Network 6.7 Power Network 6.8 Engineering Change Order 6.9 Package 6.10 Summary 6.11 Problems ReferencesChapter 7 Timing, Power, and Performance Analysis 7.1 Introduction 7.2 Buffer Insertion Mechanism 7.3 Transistor and Gate Sizing 7.3.1 Transistor sizing 7.3.2 Buffer sizing 7.3.3 Gate sizing 7.4 Timing Analysis 7.4.1 Static timing analysis 7.4.2 DTA vs. STA 7.4.3 Circuit simulation in STA 7.5 Interconnect Model and Circuit Order Reduction 7.5.1 Lumped RC vs. distributed RLC model 7.5.2 Circuit order reduction 7.6 Low Power Design 7.7 Design for Manufacture 7.8 High-level Synthesis 7.9 Performance Bound Evaluation 7.10 Summary 7.11 Problems ReferencesChapter 8 Verification and Testing 8.1 Introduction 8.2 Digital Circuits Test 8.2.1 Fault modeling 8.2.2 Fault simulation 8.2.3 Test generation for binational logic 8.2.4 Test generation for sequential logic 8.2.5 ATPG using TetraMAX 8.3 BIST 8.3.1 The concept of BIST 8.3.2 TPG 8.3.3 ORA 8.3.4 BIST architectures 8.4 Scan and Boundary Scan 8.4.1 Digital DFT for scan 8.4.2 Scan chains 8.4.3 Digital boundary scan standard- IEEE 1149.1 8.5 Summary 8.6 Problems ReferencesAppendix A A MSDAP A.1 Introduction A.2 A MSDAPAppendix B A C-Program Implementing the Algorithm of the MSDAP B.1 Introduction B.2 The MSDAP Computation Method in C-CodeAppendix C An FSM for the MSDAP Operation Mode C.1 Introduction C.2 An FSM for the Operation Mode and System SettingAppendix D A Sample Project MSDAP Report D.1 Introduction D.2 A Sample Project MSDAP Report

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