具体描述
内容简介
本书作者Pinaki Mazumder教授是IEEE Fellow和AAAS Fellow，在EDA领域有30年以上的教学、科研和工程经历。
本书汇集电子设计自动化领域包括作者在内的研究者的*新成果，聚焦超大规模集成电路布线技术，从串行与并行布线模型开始，到各种基本布线算法，兼顾芯片设计中的特定情况，重点讨论了大量的工业界实用的特殊类型布线与*新并行布线器。
本书注重基础，主要研究迷宫布线算法、总体布线算法、详细布线算法（即通道布线与开关盒布线算法等）和特殊布线算法，具有较高的通用性和实用性，有望推动超大规模集成电路布线工具的持续发展。
本书既涉及EDA领域“大家”的重要成果，也涵盖作者及其团队30多年的杰出研究，适合计算机与半导体行业从业的工程师、电子设计自动化方面的教学者阅读，也适合研究VLSI电路布局布线算法的高年级硕士生、博士生以及研究学者参考。
前言/序言
PREFACE
This handbook for routing interconnects inside a VLSI chip provides mathematical models of important classes of wiring techniques for students interested in gaining insights in integrated circuits layout automation techniques and for practicing engineers working in the field of electronic design automation (EDA). This book presents a comprehensive review on VLSI routing techniques that was undertaken in early 1990�餾 with a view to developing a generalized routing accelerator that could speed up routing chores for different styles of wiring techniques, namely, maze routing used widely for connecting different circuit blocks by finding the shortest path, channel routing used in connecting standard cells of uniform heights and variable widths arranged in the form of rows of cells, switchbox routing used in connecting surrounding multiple blocks of dissimilar aspect ratios within an enclosed routing area, and so on.
In 1988, when I started my academic career at the University of Michigan, I designed a new graduate�瞝evel course on computer�瞐ided design, EECS 527: VLSI Layout Algorithms. The course was introduced to educate graduate students and spur doctoral research in the�瞭hen burgeoning field of computer�瞐ided design (CAD) for integrated circuits (ICs) that propelled the exponential growth of integration density in VLSI chips, as postulated by Moore�餾 Law. At that time, there was no suitable textbook on the subject to teach graduate students about the state�瞣f�瞭he�瞐rt layout algorithms that were key to design complex VLSI chips. Therefore, I combed through the literature on the subject and assembled the course materials in order to teach students systematically basic underlying mathematical techniques for circuit partitioning, floor�瞤lanning, cell placement, and routing. Subsequently, I engaged my own doctoral students to expand my lecture materials in the form of comprehensive reviews.
For example, with the assistance of my doctoral student, Dr. K. Shahookar, who studied the Genetic Algorithm (GA) for VLSI cell placement techniques, I coauthored a 78�瞤age review paper, which was published in ACM Computing Surveys in June 1991. After poring over nearly a hundred publications on placement algorithms for standard cells and macro�瞔ells, I divided them into five main categories: (i) the placement by simulated annealing, (ii) the force�瞕irected placement, (iii) the placement by min�瞔ut graph algorithms, (iv) the placement by numerical optimization, and (v) the evolution�瞓ased placement. While the first two types of algorithms owe their origin to physical laws, the third and fourth are analytical techniques, and the fifth class of algorithms is derived from biological phenomena. The taxonomy of placement algorithms was created to study inherent parallelism of the different classes of algorithms. While designing the course, I realized that in order to push the mammoth potential of Moore�餾 Law, the chip design phase must be accelerated several folds by harnessing the evolving computing platforms.
In the late 80�餾, the computing platforms for the VLSI design environment were rapidly transforming from mid�瞗rame computers, namely, Digital Equipment Corporation Vax 11/780, Hewlett Packard HP 3000, and Wang Laboratories Wang VS, to the network of workstations, what is widely known as the NOW. This opportunity in hardware evolution warranted deeper insights into VLSI cell placement and routing (P&R;) techniques so that sequential algorithms that used to run on standalone mid�瞗rame computers could be rendered into parallel CAD algorithms for running efficiently on the NOW platform. Also, emergence of commercial parallel computers such as Intel hypercube and Sequent Computer System shared memory had further pushed the needs for developing parallel P&R; algorithms.
In order to promote the NOW platform for EDA research, I started working with my students to develop imaginative distributed Genetic Algorithms (GAs) for partitioning, placement and floor�瞤lanning techniques needed in VLSI chip layout automation. My research group had at that time developed an EDA tool, named Wolverines for parallel implementation of standard cell placement algorithms on the NOW platform. Since workstations are connected by a local area network (LAN) that often deploys the Ethernet to connect different workstations, communication of packets between two specific workstations generally require considerable time even when the Ethernet did not undergo collision of message packets. Because of the length of a LAN, two workstations located afar may locally sense and infer that the Ethernet is free and may launch packets asynchronously. In case, there is a collision of packets, all the senders must abandon transmission by backing off. Then they wait randomly within the range of time before attempting to transmit the packet. If a sender encounters the collision of packet again, it then waits randomly over a period of time that is twice longer than the previous time period. This exponential backing off protocol used in random�瞐ccess LAN causes a severe constraint to run parallel routing algorithms because of their fine�瞘ranularity of parallelism in contrast with placement algorithms that do not require frequent communications in parallel mode of operation over the NOW.
After realizing the key limitations of such dedicated routing accelerators that could only speed up the maze routing, my student, Dr. V. Ramachandran, who is the coauthor of this book, started looking into the possibility of developing a unified routing fabric that can be utilized to accelerate all sorts of VLSI routing algorithms. In his doctoral work, he proposed a polymorphic architecture that mainly comprises an ensemble of simple processing elements that can be configured into various connection topologies by including a suite of switches in each processing element. The highly parallel single instruction multiple data (SIMD) architecture is generally known as Content Addressable Array Parallel Processor (CAAPP) and has been originally developed for image processing applications. Specifically, Dr. Ramachandran had used the CAAPP software framework to experiment with the virtual polymorphic hardware fabric, on which different types of routing algorithms including maze, channel and switchbox were mapped as reported in Section 5.3 in this book.
My overall vision in EDA was to develop distributed networks of workstations furnished with specialized hardware accelerator board containing the polymorphic chip to accelerate different styles of VLSI routing algorithms, while Genetic Algorithms will speed up the cell placement algorithms. Due to funding constraints, in our research group we could fabricate a tiny proof of concept polymorphic chip as shown below. The purpose of this handbook is not only to introduce different styles of VLSI routing algorithms, but also to exposit the ramifications of hardware�瞫oftware co�瞕esign for such fine�瞘rained parallel algorithms over a polymorphic fabric so that various types of chip routing algorithms can be accelerated, while the placement and floor�瞤lanning algorithms will be speeded up by leveraging the intrinsic parallelism of genetic algorithms. With this vision in mind, I hope that readers will be motivated to advance the frontiers of VLSI chip design through innovating hardware�瞫oftware co�瞕esign methods as espoused in this routing handbook.
Pinaki Mazumder, Professor
Fellow of the IEEE & Fellow of the AAAS
Dept. of Elec. Eng. and Comp. Sci.
University of Michigan, Ann Arbor, USA
July 25, 2017
用户评价
这本《超大规模集成电路布线技术》对我而言，更像是一份对集成电路产业发展脉络的深入解读。它在讲解技术细节的同时，也巧妙地融入了行业发展的历史和趋势。书中对于新兴布线技术，比如三维集成电路布线、先进封装技术下的布线挑战等前瞻性内容的探讨，让我对未来的 IC 设计充满了期待。我特别喜欢其中关于设计约束管理和可制造性设计（DFM）的章节，这部分内容详细阐述了如何在设计初期就考虑生产制造的可行性，从而避免在后期出现难以解决的问题。作者通过大量的实例，展示了如何根据不同的工艺制程和设计目标，选择最合适的布线策略。这本书不仅仅是技术手册，更像是一本行业百科全书，让我能够站在更高的视角，去理解超大规模集成电路布线技术的演进和未来发展方向。它让我意识到，这个领域的发展是日新月异的，需要不断学习和掌握新的知识和技术。
评分这本《超大规模集成电路布线技术》给我带来的，是一种前所未有的“结构化思维”训练。它并非枯燥的技术术语堆砌，而是以一种系统化的方式，引导读者去理解芯片内部庞大而精密的“网络”是如何构建起来的。书中对各种布线工具和EDA（电子设计自动化）软件的原理性介绍，让我对这些强大的辅助工具有了更深的认识，明白它们并非万能，而是需要工程师具备扎实的理论基础才能发挥最大效用。我尤其喜欢书中关于物理验证和时序收敛的章节，这部分内容详细阐述了在实际流片过程中，如何通过反复的检查和优化，来确保芯片的性能达到设计目标。它让我明白，一个成功的芯片设计，是设计、布线、验证等各个环节协同作用的结果。作者通过大量的图例和流程图，将复杂的布线流程可视化，使得读者能够清晰地把握每一个步骤的逻辑和目标。这本书的价值在于，它不仅仅教你如何“画线”，更教你如何“思考”，如何从宏观到微观，一步步构建起满足复杂需求的集成电路。
评分这本书就像是一本给工程师的“圣经”，对于想要在IC设计领域深耕的人来说，绝对是不可或缺的宝藏。它并没有停留于表面的介绍，而是非常深入地探讨了超大规模集成电路布线领域中的核心难题和前沿技术。我印象最深的是关于电源完整性（PI）和信号完整性（SI）的分析部分，这不仅仅是理论上的阐述，更包含了大量的仿真技巧和实际遇到的问题解决方案。书中详细介绍了各种潜在的信号干扰源，比如串扰、地弹、电源噪声等，以及如何通过精巧的布线策略来规避这些问题。而且，它还讲解了在高速数字电路和模拟电路中，布线设计所面临的独特挑战，并提供了切实可行的优化方法。我特别欣赏作者在讨论先进工艺节点下的布线技术时，对寄生效应的深入剖析，这对于理解当今高性能芯片的设计至关重要。这本书不仅仅是技术资料的堆砌，更体现了作者丰富的实践经验和深厚的理论功底。它让我在面对复杂的布线问题时，不再感到束手无策，而是能够从容地分析原因，并找到最优的解决方案。
评分一本让我彻底拓宽了视野的工业巨著！我一直对电子产品的“幕后英雄”——那些微小的、纵横交错的电路布线——充满好奇，但市面上真正深入浅出的技术书籍却寥寥无几。直到我翻开这本《超大规模集成电路布线技术》，才算真正拨开了迷雾。从最基础的布线规则和设计流程讲起，作者用一种极其耐心且条理清晰的方式，将复杂的概念层层剥开。我特别喜欢书中关于时序约束和信号完整性处理的章节，虽然听起来很专业，但通过丰富的图示和具体的案例分析，即使是我这样的初学者也能理解其中的精髓。它不仅仅是讲解了“怎么做”，更深入探讨了“为什么这么做”，让我理解了每一个设计决策背后的考量和权衡。书中对不同布线算法的比较分析也让我大开眼界，原来在看似简单的线条背后，隐藏着如此多的优化和智慧。读完这本书，我感觉自己对芯片的理解已经上升到了一个全新的维度，仿佛能看到那些电子在内部奔腾的轨迹，充满了敬畏感。它让我明白，每一个微小的电子元件，都承载着工程师们无数的心血和智慧。
评分这是一本能够点燃你对微观世界探索欲望的奇书。在翻阅之前，我对“布线”的理解可能还停留在电线连接电器那么简单，但这本书彻底颠覆了我的认知。它将布线技术提升到了艺术和科学的高度，展示了如何在一个方寸大小的芯片上，实现数以亿计的晶体管之间的精密连接。书中关于功耗和热量的布线考量，让我意识到，除了性能，工程师们还需要在有限的空间内，处理好能源的利用和散热问题。我特别欣赏书中对不同布线算法的详尽描述，比如从网格布线到全局布线再到详细布线，每一步都有其独特的优化目标和面临的挑战。作者通过鲜活的案例，揭示了这些算法在实际应用中的巧妙之处，以及它们如何影响芯片的最终性能和功耗。这本书让我明白了，每一个微小的电流路径，都经过了精密的计算和优化，其背后凝聚了无数工程师的智慧和汗水。读完它，我感觉自己仿佛拥有了一双能够“看见”芯片内部运作的眼睛。
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