具體描述
內容簡介
本書作者Pinaki Mazumder教授是IEEE Fellow和AAAS Fellow，在EDA領域有30年以上的教學、科研和工程經曆。
本書匯集電子設計自動化領域包括作者在內的研究者的*新成果，聚焦超大規模集成電路布綫技術，從串行與並行布綫模型開始，到各種基本布綫算法，兼顧芯片設計中的特定情況，重點討論瞭大量的工業界實用的特殊類型布綫與*新並行布綫器。
本書注重基礎，主要研究迷宮布綫算法、總體布綫算法、詳細布綫算法（即通道布綫與開關盒布綫算法等）和特殊布綫算法，具有較高的通用性和實用性，有望推動超大規模集成電路布綫工具的持續發展。
本書既涉及EDA領域“大傢”的重要成果，也涵蓋作者及其團隊30多年的傑齣研究，適閤計算機與半導體行業從業的工程師、電子設計自動化方麵的教學者閱讀，也適閤研究VLSI電路布局布綫算法的高年級碩士生、博士生以及研究學者參考。
前言/序言
PREFACE
This handbook for routing interconnects inside a VLSI chip provides mathematical models of important classes of wiring techniques for students interested in gaining insights in integrated circuits layout automation techniques and for practicing engineers working in the field of electronic design automation (EDA). This book presents a comprehensive review on VLSI routing techniques that was undertaken in early 1990�餾 with a view to developing a generalized routing accelerator that could speed up routing chores for different styles of wiring techniques, namely, maze routing used widely for connecting different circuit blocks by finding the shortest path, channel routing used in connecting standard cells of uniform heights and variable widths arranged in the form of rows of cells, switchbox routing used in connecting surrounding multiple blocks of dissimilar aspect ratios within an enclosed routing area, and so on.
In 1988, when I started my academic career at the University of Michigan, I designed a new graduate�瞝evel course on computer�瞐ided design, EECS 527: VLSI Layout Algorithms. The course was introduced to educate graduate students and spur doctoral research in the�瞭hen burgeoning field of computer�瞐ided design (CAD) for integrated circuits (ICs) that propelled the exponential growth of integration density in VLSI chips, as postulated by Moore�餾 Law. At that time, there was no suitable textbook on the subject to teach graduate students about the state�瞣f�瞭he�瞐rt layout algorithms that were key to design complex VLSI chips. Therefore, I combed through the literature on the subject and assembled the course materials in order to teach students systematically basic underlying mathematical techniques for circuit partitioning, floor�瞤lanning, cell placement, and routing. Subsequently, I engaged my own doctoral students to expand my lecture materials in the form of comprehensive reviews.
For example, with the assistance of my doctoral student, Dr. K. Shahookar, who studied the Genetic Algorithm (GA) for VLSI cell placement techniques, I coauthored a 78�瞤age review paper, which was published in ACM Computing Surveys in June 1991. After poring over nearly a hundred publications on placement algorithms for standard cells and macro�瞔ells, I divided them into five main categories: (i) the placement by simulated annealing, (ii) the force�瞕irected placement, (iii) the placement by min�瞔ut graph algorithms, (iv) the placement by numerical optimization, and (v) the evolution�瞓ased placement. While the first two types of algorithms owe their origin to physical laws, the third and fourth are analytical techniques, and the fifth class of algorithms is derived from biological phenomena. The taxonomy of placement algorithms was created to study inherent parallelism of the different classes of algorithms. While designing the course, I realized that in order to push the mammoth potential of Moore�餾 Law, the chip design phase must be accelerated several folds by harnessing the evolving computing platforms.
In the late 80�餾, the computing platforms for the VLSI design environment were rapidly transforming from mid�瞗rame computers, namely, Digital Equipment Corporation Vax 11/780, Hewlett Packard HP 3000, and Wang Laboratories Wang VS, to the network of workstations, what is widely known as the NOW. This opportunity in hardware evolution warranted deeper insights into VLSI cell placement and routing (P&R;) techniques so that sequential algorithms that used to run on standalone mid�瞗rame computers could be rendered into parallel CAD algorithms for running efficiently on the NOW platform. Also, emergence of commercial parallel computers such as Intel hypercube and Sequent Computer System shared memory had further pushed the needs for developing parallel P&R; algorithms.
In order to promote the NOW platform for EDA research, I started working with my students to develop imaginative distributed Genetic Algorithms (GAs) for partitioning, placement and floor�瞤lanning techniques needed in VLSI chip layout automation. My research group had at that time developed an EDA tool, named Wolverines for parallel implementation of standard cell placement algorithms on the NOW platform. Since workstations are connected by a local area network (LAN) that often deploys the Ethernet to connect different workstations, communication of packets between two specific workstations generally require considerable time even when the Ethernet did not undergo collision of message packets. Because of the length of a LAN, two workstations located afar may locally sense and infer that the Ethernet is free and may launch packets asynchronously. In case, there is a collision of packets, all the senders must abandon transmission by backing off. Then they wait randomly within the range of time before attempting to transmit the packet. If a sender encounters the collision of packet again, it then waits randomly over a period of time that is twice longer than the previous time period. This exponential backing off protocol used in random�瞐ccess LAN causes a severe constraint to run parallel routing algorithms because of their fine�瞘ranularity of parallelism in contrast with placement algorithms that do not require frequent communications in parallel mode of operation over the NOW.
After realizing the key limitations of such dedicated routing accelerators that could only speed up the maze routing, my student, Dr. V. Ramachandran, who is the coauthor of this book, started looking into the possibility of developing a unified routing fabric that can be utilized to accelerate all sorts of VLSI routing algorithms. In his doctoral work, he proposed a polymorphic architecture that mainly comprises an ensemble of simple processing elements that can be configured into various connection topologies by including a suite of switches in each processing element. The highly parallel single instruction multiple data (SIMD) architecture is generally known as Content Addressable Array Parallel Processor (CAAPP) and has been originally developed for image processing applications. Specifically, Dr. Ramachandran had used the CAAPP software framework to experiment with the virtual polymorphic hardware fabric, on which different types of routing algorithms including maze, channel and switchbox were mapped as reported in Section 5.3 in this book.
My overall vision in EDA was to develop distributed networks of workstations furnished with specialized hardware accelerator board containing the polymorphic chip to accelerate different styles of VLSI routing algorithms, while Genetic Algorithms will speed up the cell placement algorithms. Due to funding constraints, in our research group we could fabricate a tiny proof of concept polymorphic chip as shown below. The purpose of this handbook is not only to introduce different styles of VLSI routing algorithms, but also to exposit the ramifications of hardware�瞫oftware co�瞕esign for such fine�瞘rained parallel algorithms over a polymorphic fabric so that various types of chip routing algorithms can be accelerated, while the placement and floor�瞤lanning algorithms will be speeded up by leveraging the intrinsic parallelism of genetic algorithms. With this vision in mind, I hope that readers will be motivated to advance the frontiers of VLSI chip design through innovating hardware�瞫oftware co�瞕esign methods as espoused in this routing handbook.
Pinaki Mazumder, Professor
Fellow of the IEEE & Fellow of the AAAS
Dept. of Elec. Eng. and Comp. Sci.
University of Michigan, Ann Arbor, USA
July 25, 2017
用戶評價
這本《超大規模集成電路布綫技術》對我而言，更像是一份對集成電路産業發展脈絡的深入解讀。它在講解技術細節的同時，也巧妙地融入瞭行業發展的曆史和趨勢。書中對於新興布綫技術，比如三維集成電路布綫、先進封裝技術下的布綫挑戰等前瞻性內容的探討，讓我對未來的 IC 設計充滿瞭期待。我特彆喜歡其中關於設計約束管理和可製造性設計（DFM）的章節，這部分內容詳細闡述瞭如何在設計初期就考慮生産製造的可行性，從而避免在後期齣現難以解決的問題。作者通過大量的實例，展示瞭如何根據不同的工藝製程和設計目標，選擇最閤適的布綫策略。這本書不僅僅是技術手冊，更像是一本行業百科全書，讓我能夠站在更高的視角，去理解超大規模集成電路布綫技術的演進和未來發展方嚮。它讓我意識到，這個領域的發展是日新月異的，需要不斷學習和掌握新的知識和技術。
評分這本書就像是一本給工程師的“聖經”，對於想要在IC設計領域深耕的人來說，絕對是不可或缺的寶藏。它並沒有停留於錶麵的介紹，而是非常深入地探討瞭超大規模集成電路布綫領域中的核心難題和前沿技術。我印象最深的是關於電源完整性（PI）和信號完整性（SI）的分析部分，這不僅僅是理論上的闡述，更包含瞭大量的仿真技巧和實際遇到的問題解決方案。書中詳細介紹瞭各種潛在的信號乾擾源，比如串擾、地彈、電源噪聲等，以及如何通過精巧的布綫策略來規避這些問題。而且，它還講解瞭在高速數字電路和模擬電路中，布綫設計所麵臨的獨特挑戰，並提供瞭切實可行的優化方法。我特彆欣賞作者在討論先進工藝節點下的布綫技術時，對寄生效應的深入剖析，這對於理解當今高性能芯片的設計至關重要。這本書不僅僅是技術資料的堆砌，更體現瞭作者豐富的實踐經驗和深厚的理論功底。它讓我在麵對復雜的布綫問題時，不再感到束手無策，而是能夠從容地分析原因，並找到最優的解決方案。
評分這本《超大規模集成電路布綫技術》給我帶來的，是一種前所未有的“結構化思維”訓練。它並非枯燥的技術術語堆砌，而是以一種係統化的方式，引導讀者去理解芯片內部龐大而精密的“網絡”是如何構建起來的。書中對各種布綫工具和EDA（電子設計自動化）軟件的原理性介紹，讓我對這些強大的輔助工具有瞭更深的認識，明白它們並非萬能，而是需要工程師具備紮實的理論基礎纔能發揮最大效用。我尤其喜歡書中關於物理驗證和時序收斂的章節，這部分內容詳細闡述瞭在實際流片過程中，如何通過反復的檢查和優化，來確保芯片的性能達到設計目標。它讓我明白，一個成功的芯片設計，是設計、布綫、驗證等各個環節協同作用的結果。作者通過大量的圖例和流程圖，將復雜的布綫流程可視化，使得讀者能夠清晰地把握每一個步驟的邏輯和目標。這本書的價值在於，它不僅僅教你如何“畫綫”，更教你如何“思考”，如何從宏觀到微觀，一步步構建起滿足復雜需求的集成電路。
評分一本讓我徹底拓寬瞭視野的工業巨著！我一直對電子産品的“幕後英雄”——那些微小的、縱橫交錯的電路布綫——充滿好奇，但市麵上真正深入淺齣的技術書籍卻寥寥無幾。直到我翻開這本《超大規模集成電路布綫技術》，纔算真正撥開瞭迷霧。從最基礎的布綫規則和設計流程講起，作者用一種極其耐心且條理清晰的方式，將復雜的概念層層剝開。我特彆喜歡書中關於時序約束和信號完整性處理的章節，雖然聽起來很專業，但通過豐富的圖示和具體的案例分析，即使是我這樣的初學者也能理解其中的精髓。它不僅僅是講解瞭“怎麼做”，更深入探討瞭“為什麼這麼做”，讓我理解瞭每一個設計決策背後的考量和權衡。書中對不同布綫算法的比較分析也讓我大開眼界，原來在看似簡單的綫條背後，隱藏著如此多的優化和智慧。讀完這本書，我感覺自己對芯片的理解已經上升到瞭一個全新的維度，仿佛能看到那些電子在內部奔騰的軌跡，充滿瞭敬畏感。它讓我明白，每一個微小的電子元件，都承載著工程師們無數的心血和智慧。
評分這是一本能夠點燃你對微觀世界探索欲望的奇書。在翻閱之前，我對“布綫”的理解可能還停留在電綫連接電器那麼簡單，但這本書徹底顛覆瞭我的認知。它將布綫技術提升到瞭藝術和科學的高度，展示瞭如何在一個方寸大小的芯片上，實現數以億計的晶體管之間的精密連接。書中關於功耗和熱量的布綫考量，讓我意識到，除瞭性能，工程師們還需要在有限的空間內，處理好能源的利用和散熱問題。我特彆欣賞書中對不同布綫算法的詳盡描述，比如從網格布綫到全局布綫再到詳細布綫，每一步都有其獨特的優化目標和麵臨的挑戰。作者通過鮮活的案例，揭示瞭這些算法在實際應用中的巧妙之處，以及它們如何影響芯片的最終性能和功耗。這本書讓我明白瞭，每一個微小的電流路徑，都經過瞭精密的計算和優化，其背後凝聚瞭無數工程師的智慧和汗水。讀完它，我感覺自己仿佛擁有瞭一雙能夠“看見”芯片內部運作的眼睛。
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